The present invention relates generally to scan testing of integrated circuit and more particularly to scan testing of single-level or multi-level nested integrated circuits.
Integrated circuits (ICs) generally and application specific integrated circuits (ASICs) specifically can be programmed to perform any number of functions. In order to test them, circuitry separate from the programmed functions is included specifically for testing. The test circuitry requires input and output ports that are separate from the input and output ports of the programmed functions. During normal operations, the functional circuitry operates, and during test operations, a separate set of test circuitry using the test inputs and outputs are used.
Cores are also becoming more common as computer-aided drawing (CAD) tools are used to design complete circuits. However, CAD tools have a capacity that is a fraction of the size of a completed circuit. Such large projects can be simplified when designed in terms of smaller cores and sub-cores rather than as one monolithic chip. Splitting a design into several smaller pieces simplifies the design and enables each part to be individually tested, the final product consisting of multiple interconnected core sections.
Additionally, the purchase of intellectual property frequently sees individual cores and sub-cores being purchased from outside vendors and being embedded into a chip rather than whole chips designs.
Each core and sub-core has its own test input and output ports and needs to be tested individually, without interference from adjacent cores or sub-cores, as well as part of the whole system. These test ports are part of a test-related element called a xe2x80x9cwrapper cell,xe2x80x9d the circuitry attached to the functional elements of a core to provide paths for test data to flow. A wrapper cell normally consists of a flip-flop and a multiplexer, and is able to function in a functional mode and a test mode. In the functional mode, the wrapper cell is transparent and normal functional signals are passed through the multiplexer to the functional core. In the test mode, the wrapper cell changes the input signal causing the test input to be passed through the multiplexer.
Many wrapper cells are chained together in a chip register in order to scan test data in and out of the circuit in a method referred to as xe2x80x9cscan testingxe2x80x9d. There are many different schemes for scan testing, but the predominant method is the monolithic scan path approach where the scan elements, such as the wrapper cell and scan chains, are connected in a straight-path, serial manner. While this has the ability to send and receive test data from every core and sub-core in a chip, it is also slow since testing one scan element in the chain requires moving data through every scan element in the serial chain. Further, it is not possible with this approach to select specific internal scan chains or subsets of internal scan chains for loading or unloading test data which makes it difficult to pinpoint problems.
Another approach is to connect scan-in ports directly to scan-in terminals for each core. This makes it possible to select specific internal scan chains or subsets of internal scan chains, however, this is difficult to implement because the total number of available scan ports at the integrated circuit chip boundary typically are exceeded by the total number of scan paths requiring access to these ports, and further because impractical amounts of wiring is required.
As the complexity of integrated circuits increase and more system-on-a-chip devices come into use, the need to find an efficient method for the scan testing of single-level and multi-level integrated circuits becomes more and more imperative.
The present invention provides a scan path structure for integrated circuits which contain one or more cores or levels of sub-cores embedded within the costs. Circuitry is provided to permit scan testing of scan elements, such as scan wrapper cells and scan chains, in the cores and sub-cores by providing scan paths which share access to limited numbers of scan test ports of the integrated circuit under test. This solves the problem of having insufficient scan ports at the integrated circuit boundaries for the increasingly higher number of scan paths which require access to these scan ports.
The present invention provides a reconfigurable scan path structure for integrated circuits which contain one or more cores or levels of sub-cores embedded within the cores. Logic circuitry is provided to permit scan testing of scan elements, such as scan wrapper cells and scan chains, in the cores and sub-cores by providing alternate scan paths which share access to limited numbers of scan test ports of the integrated circuit under test. This solves the problem of having sufficient scan ports at the integrated circuit boundaries for the increasingly higher number of scan ports which require access to these scan ports.
The present invention further provides a reconfigurable scan path structure for integrated circuits having global scan-in buses and which contain one or more cores or levels of sub-cores embedded within the cores. Logic circuitry is connected to the global buses which pass through the cores and sub-cores requiring scan access and allow connections to permit scan testing of scan elements in the cores and sub-cores by providing alternate scan paths which share access to limited data test ports of the integrated circuit under test. This solves the problem of having insufficient scan ports at the integrated circuit boundary for the increasingly higher number of scan paths which require access to these scan ports.
The present invention further provides a reconfigurable scan path structure for integrated circuits which do not have global scan-in buses and which contain one or more cores of levels of sub-cores embedded within the cores. Logic circuitry is provided to permit scan testing of scan elements in the cores and sub-cores by providing scan-in data through the logic circuitry and by providing alternate scan paths which share access to limited data test ports of the integrated circuit under test. This solves the problem of having sufficient scan ports at the integrated circuit boundary for the increasingly higher number of scan paths which require access to these scan ports and eliminates the need for a global bus.
The present invention further provides a reconfigurable scan path structure for integrated circuit which contain one or more cores, sub-cores embedded within the cores, or multi-levels of sub-cores within sub-cores. Logic circuitry is provided to permit scan testing of scan elements in the cores, sub-cores and sub-sub-cores by providing alternate scan paths which share access to limited data test ports of the integrated circuit under test. This solves the problem of having insufficient scan ports at the integrated circuit boundary for the increasingly higher number of scan paths which require access to these scan ports, and further increases the efficiency of scan testing.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.